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I'd like to write a Radare2 plugin for a legacy 48-bit word-oriented CPU which has two 24-bit instructions per word, and, naturally, uses word addressing. I wrote a disassembler plugin which prints the instructions, but it is hard to follow the control flow. It would be nice to have word offsets printed on the left instead of the byte offsets, and to be able to specify the way raw instructions are printed.

Is it possible in the current version?

Instead of

        0x00001800    002041       mode 101
        0x00001803    2a04b0       seti 2260(r2)
        0x00001806    aa0542       seti 2502(r12)
        0x00001809    6a7fd2       seti 77722(r6) ; 0x0000007f 
        0x0000180c    00855f       ld   2537
        0x0000180f    000585       st   2605
        0x00001812    01e041       shr  1
        0x00001815    6005b4       st   2664(r6)
        0x00001818    6f8403       loop 2003(r6)

I would like, ideally, to get something like

           02000 00 002 0101    mode 101
                 02 24 02260    seti 2260(r2)
           02001 12 24 02502    seti 2502(r12)
                 06 24 77722    seti 77722(r6)
           02002 00 010 2537    ld   2537
                 00 000 2605    st   2605
           02003 00 036 0101    shr  1
                 06 000 2664    st   2664(r6)
           02004 06 37 02003    loop 2003(r6)
                 ...

(The 0x0000007f comment is likely due to the x86 analyzer which kicks in by default, is that right?)

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    this question should be probably asked at radare's development site/mailing list
    – Igor Skochinsky ♦
    Commented Feb 2, 2017 at 18:06
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    On the footnote question: most likely, yes. 6A 7F translates to push 7Fh. Weird, if you selected a different CPU. It must be hardcoded elsewhere.
    – Jongware
    Commented Feb 2, 2017 at 21:45
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    Usage questions can probably be answered by someone here, development questions I think are better asked to devs directly.
    – Igor Skochinsky ♦
    Commented Feb 3, 2017 at 6:40
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    @IgorSkochinsky collecting the answer to questions like these seems a good reason to have this question here. Also, radare is actually open source and does not sell support cough
    – Nordwald
    Commented Feb 3, 2017 at 7:00
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    I'm not saying this is off-topic, just suggesting that devs are in a better position to answer it.
    – Igor Skochinsky ♦
    Commented Feb 4, 2017 at 15:54

2 Answers 2

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I dont know what is a word based arch. but if you refer to fixed size instructions yes, in r2 you can define the alignment, minimum and maximum instruction sizes and default size of invalid instructions. So yep you can do all this stuff with radare.

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  • A word-based arch is one with the least addressable unit of memory being a word rather than a byte.
    – Leo B.
    Commented Feb 5, 2017 at 6:44
  • like arm or mips?
    – pancake
    Commented Feb 23, 2017 at 23:02
  • I don't think so. On a typical RISC architecture, the least loadable in a single instruction unit of memory may be a word, but addressing the RAM is still done in terms of bytes. The word-oriented machines address memory in terms of words, and the word size doesn't have to be a power of 2, or an even number of bits, or a composite number of bits.
    – Leo B.
    Commented May 5, 2017 at 7:39
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I will fill an issue in github because that is the place this kind of things should be posted. This change in the disasm can be done in 5-10 minutes, but i would like to have more details on which is the that arch, where can I find this plugin, etc.

https://github.com/radare/radare2/issues/9813

Thanks

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1
  • Thank you; now I have to revive that code and to post it somewhere.
    – Leo B.
    Commented Apr 6, 2018 at 14:38

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