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RISC instruction set architecture (ISA). It is commonly used in embedded devices such as set top boxes and networking gear. Many university-level computer architecture classes use the MIPS ISA due to its relative simplicity.

MIPS is a common RISC (Reduced Instruction Set Computer) ISA (Instruction Set Architecture), one of the first of its kind. Currently, MIPS can refer to both a hardware implementation of the ISA and the assembly language itself. The tag is applicable to both, although most questions will probably relate to the assembly language. MIPS originally stood for "Microprocessor without Interlocked Pipeline Stages", though modern MIPS implementations now have interlocked pipeline stages.

MIPS processors come in both big-endian and little-endian (often referred to as mipsel) flavours. It is likely that MIPS will be encountered when reverse engineering consumer grade routers, IP cameras, or Linux systems based on small form factors such as the Carambola2 or the Vocore, including many systems using Broadcom, Atheros and Ralink system on chips.

  • Wikipedia overview: history, CPU families, instruction format, register usage conventions
  • MIPS 32 architecture: manufacturer summary and links to reference manuals
  • MIPS 64 architecture: ditto for 64-bit CPUs (navbar has links for microMIPS, DSP ASE, MT, SmartMIPS, MIPS16, MIPS-3D, MCU ASE)