Questions tagged [sparc]

Scalable Processor ARChitecture is a RISC ISA designed by Sun Microsystems in the late 1980s. The initial design was 32-bits but was lately extended to handle 64-bits operations.

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2answers
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Where can I find documentation for the name mangling scheme used by SunPro CC

I have a few SPARC binaries that have been compiled with what seems to be the SunPro CC compiler. The symbols in the binary are referring to a very early C++ implementation (pre-namespaces) and look ...
3
votes
1answer
125 views

What is the encoding format for unconditional Jumps on SPARC/SPARC64?

I am trying to figure out the encoding for unconditional JMPs on SPARC, i.e the JMP. After disassembling a few binaries. In my IDA disassembly the encoding for JMP %g1 is: 81 c0 40 00 Digging ...
0
votes
1answer
174 views

IDAPro arcompact difficulties

I'm having some difficulties disassembling an arcompact program with IDAPro. The program has a large number of code banks/overlays and a rather overused manager that can branch to any function in any ...
4
votes
1answer
606 views

On SPARC, what happens when a branch is placed in the branch-delay slot of another branch?

Our team recently had to look at SPARC assembly specifications, the problem is that I do not have a SPARC processor to try things on it (I should set up a simulator or get one of these old Sparc ...
4
votes
1answer
8k views

Reverse engineering flexlm license management

I have a 3D driver from the early 90's for Solaris 2.5-2.6 Sparc that uses flexlm to handle license management. How would I go about either circumventing or removing it for computer archeology/hobby ...
5
votes
1answer
452 views

Reverse engineering a Solaris driver

I have several Solaris 2.6 era drivers I would like to reverse engineer. I have a Sparc disassembler which provides some info but it isn't maintained anymore so I think it may not give me all the ...