I'm trying to understand the syntax of the IT instruction that is to be used to enable conditional execution of instructions on ARM, in Thumb2 mode.

The way I understand it, the bits in the CPSR register along with the IT instruction make conditional execution possible in Thumb mode. If I were writing some Thumb2 code perhaps I could go about following the process mentioned below.

Lets say I have 4 conditional instructions(the maximum limit suported by IT).

  1. First, I write down by conditional instructions. Lets say the prefixes for the four instructions are CLZNE.W, CLZEQ.W, ADDEQ, ADDNEQ.
  2. Now before the conditional instructions I add an instruction of the form ITEEE NE. The NE is added as the first instruction has an NE. The EEE following the IT are added as the last 3 instructions are the converse of an NE. Is this how assembly programmers write conditional thumb2 ARM code? Is my understanding of the process correct?
  3. Why is the condition encoded in both IT and the instructions that follow?
  • 1
    Usually, when I am not sure about the semantics of an ARM instruction, I use this website. It always give you a good insight of what really does the instruction.
    – perror
    May 27, 2015 at 10:14

2 Answers 2


As far as I understand you described the process of using IT instructions correctly. This is exactly how one of compilers I worked with works.


According to (for example) ARM Architecture Reference Manual document conditions are not encoded in most of conditionally executed Thumb instructions (except of jumps and some others) and it is the thing that defines the reason for IT instruction and all its variants existence.

Unfortunately I couldn't find exact Thumb 2 encoding reference, but I think that it behaves the same as in Thumb.


Yes, it is correct,both thumb and thumb II instructions I looked to does not have condition field (for example addition instructions and other ALU related things). The document I found it in is ARMv7-A -R Architecture Reference Manual, its download requires registration. So regarding your question number 3 - conditions in IT compliant operations are definitely not encoded in instruction itself.


The condition codes displayed after the instructions is a convenience feature of the disassembler (deduced from the preceding IT instruction), the individual Thumb-2 instructions do not encode the condition codes. Adding condition codes even if they're not encoded is also the practice recommended by ARM when writing UAL assembly. This serves two purposes:

  1. The assembler can check that the IT instruction matches the following conditional-suffixed instructions (e.g. all T instructions use the same condition as IT itself and all E ones use the opposite one),and no conditional instructions appear outside of the IT range.

  2. The same assembly can be used when assembling for ARM mode - the IT instruction is ignored (or hidden by an ifdef) and conditional instructions are assembled as regular conditional ARM instructions.

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