I'm trying to understand the syntax of the
IT instruction that is to be used to enable conditional execution of instructions on ARM, in Thumb2 mode.
The way I understand it, the bits in the CPSR register along with the
IT instruction make conditional execution possible in Thumb mode. If I were writing some Thumb2 code perhaps I could go about following the process mentioned below.
Lets say I have 4 conditional instructions(the maximum limit suported by
- First, I write down by conditional instructions. Lets say the prefixes for the four instructions are
- Now before the conditional instructions I add an instruction of the form
ITEEE NE. The NE is added as the first instruction has an NE. The
EEEfollowing the IT are added as the last 3 instructions are the converse of an
NE. Is this how assembly programmers write conditional thumb2 ARM code? Is my understanding of the process correct?
- Why is the condition encoded in both
ITand the instructions that follow?