I'm writing a disassembler for ARM opcodes and I'm struggling with a particular encoding. The offending instruction is
E1F120D1. I think I've followed the instructions closely, and expect the disassemble to be
mvns r2,r1 but trying it on http://www.onlinedisassembler.com gives me
It seems like the low-order
20D1 in the instruction is causing online disassembler ti switch from
ldrsb. Is this a bug in the disassembler -- not likely -- or my misunderstanding the instruction encodings in the manual?