I'm writing a disassembler for ARM opcodes and I'm struggling with a particular encoding. The offending instruction is E1F120D1. I think I've followed the instructions closely, and expect the disassemble to be mvns r2,r1 but trying it on http://www.onlinedisassembler.com gives me ldsrb r2,[r1,#1]!.

It seems like the low-order 20D1 in the instruction is causing online disassembler ti switch from mvn to ldrsb. Is this a bug in the disassembler -- not likely -- or my misunderstanding the instruction encodings in the manual?

2 Answers 2


If you look at the ARM Architecture Reference Manual, you should be able to see that Chapter A5 takes you through the decoding of ARM instructions.

Starting with table A5-1, your instruction has -

cond (31-28) = 1110
op1 (27-25) =  000

This matches

cond = not 1111, op1 = 00x  => Data Processing & Miscellaneous instructions (A5.2)

Then for table A5-2 in section A5.2, your instruction has -

op (25) = 0
op1 (24-20) = 11111
op2 (7-4) = 1101

The encoding that matches these bits is -

op = 0, op1 = not 0xx1x, op2 = 11x1 => Extra load/store instructions (A5.2.8)

Finally for table A5-10 in section A5.2.8, your instruction has -

op2 (6-5) = 10
op1 (24-20) = 11111
Rn (19-16) = 0001

This matches

op2 = 10, op1 = xx1x1, Rn = not 1111 => LDRSB (immediate)

So, yes, bits 7-4 definitely affect the decoding of this instruction.

  • Indeed this correct. My mistake was using a very old reference for the ARM architecture, where the LDRSB instruction was not implemented yet. Commented May 11, 2015 at 11:40

This is LDRSB:

Cond 000 PU0W L Rn Rd 0 0 0 0 Rm

This is MVN:

Cond 001 1111 ...

The difference is in the I register. MVN is register to register only.

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