This can be a little awkward from time to time.
There are several ways this can pan out. In approximate order of lazyness:
- You allow the router to provide power and the Bus Pirate attempts to drive the CS, clock, MOSI and reads MISO.
The problem here will be that you need the master CS and clock to be in a high-impedance state for this to work. Because the master knows it will be driving these signals, this isn't always the case. For power saving purposes though, a lot of masters will let these go high impedance.
You also rely on the master not responding in anyway to unprompted changes in MISO. If the master sees a change of MISO and responds, you will end up with garbage.
- You allow the Bus Pirate to provide power.
Sometimes this works when 1 fails. This relies on the circuit somehow isolating the power supply to the memory device from the master of the SPI bus. You end up powering the memory device and not the master. Bigger boards sometimes isolate the power supplies, but often you'll just end up in the same situation as 1.
- Hope the device reads the entire useful memory of the device and sniff bus.
Quite a lot of routers using SPI memory for settings or firmware read the entire device sequentially at start-up, or if you issue a command to write settings to the device they will write it out. Alternatively, most devices will eventually read all of the memory addresses they actually need, and you can sniff these and reconstruct the memory.
- Cut the power between the memory device and master, use Bus Pirate for power.
Sometimes there is a very easy place to cut the power between the memory device and master. You probably want it to be repairable.
- Desolder the entire memory device and dump it.
If all the others fail, you need to do this.