3

Olly, specifically, will only accept the last prefix it finds if there are more than one from the same group. For example

lock rep add dword ptr[eax],eax    ; f0 f3 01 00

becomes

???                           ; f0                 
rep add dword ptr[eax],eax    ; f3 01 00

Page 28 of the Intel architecture manual simply states "it is only useful to include up to one prefix code from each of the four groups ..." but no where does it say it's required to only have, at most, one from each group. Yes, there are cases where some of the prefixes are required, must not be present, or are only valid depending on the instruction, but I'm not referring to any of those scenarios.

I'm choosing to interpret Intel's guidance as meaning "it's valid but there aren't many reasons to do it" and I'll continue to leave the prefix listed with the instruction (again, barring any specific rules that say otherwise.)

Is this the correct way to handle the situation or should I be doing something different?

8

The general rule of thumb is that every prefix is applied in sequence. For example, two 66 prefixes cancel each other, and 66 66 66 is the same as single 66.

EDIT: it seems I was wrong, and repeated prefixes are ignored.

The situation becomes somewhat muddled for SSE instructions where some prefixes are mandatory and some are optional, and their order may matter. For example, if both F2 and F3 are used with an SSE instruction, then the last one "wins", and 66 is ignored if other prefixes are present (except for a few instructions like CRC32).

66 f3 f2 0f 59 ff     ; mulsd xmm7, xmm7
66 f2 f3 0f 59 ff     ; mulss xmm7, xmm7
66 0f 59 ff           ; mulpd xmm7, xmm7
f2 66 0f 59 ff        ; mulsd xmm7, xmm7

In general, docs don't describe the corner cases very well. So the best thing to do is to put some bytes into a file, run it on the actual CPU, and observe what happens.

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