The following code snippet is the first few assembly instructions of a function. The code runs on armv8a. SUB SP, SP, #0x170 is the first assembly instruction of the function. Please note the instruction, FCMP S0, #0.0 . My question is, register S0 is used without initialization. How is this possible?

Is there any assembly instruction that implicitly modifies S0 ?

.text:00000000000CDCF0                 SUB             SP, SP, #0x170
.text:00000000000CDCF4                 MOV             X2, #1
.text:00000000000CDCF8                 MOV             X3, X2
.text:00000000000CDCFC                 STR             D8, [SP,#0x170+var_120]
.text:00000000000CDD00                 STP             X23, X24, [SP,#0x170+var_150]
.text:00000000000CDD04                 MOV             X23, X0
.text:00000000000CDD08                 MOV             X0, #0
.text:00000000000CDD0C                 STP             X21, X22, [SP,#0x170+var_160]
.text:00000000000CDD10                 STP             X19, X20, [SP,#0x170+var_170]
.text:00000000000CDD14                 STP             X25, X26, [SP,#0x170+var_140]
.text:00000000000CDD18                 STP             X27, X30, [SP,#0x170+var_130]
.text:00000000000CDD1C                 ADD             X21, SP, #0x170+var_10
.text:00000000000CDD20                 ADD             X22, SP, #0x170+var_8
.text:00000000000CDD24                 LDRSW           X1, [X23,#0x40]
.text:00000000000CDD28                 MOV             X4, X21
.text:00000000000CDD2C                 MOV             X5, X22
.text:00000000000CDD30                 BL              GOMP_loop_dynamic_start
.text:00000000000CDD34                 UXTB            W0, W0
.text:00000000000CDD38                 CBZ             W0, loc_CE0B8
.text:00000000000CDD3C                 FMOV            S8, #1.0
.text:00000000000CDD40 loc_CDD40                               ;
.text:00000000000CDD40                 LDR             X24, [SP,#0x170+var_10]
.text:00000000000CDD44                 LDR             W20, [SP,#0x170+var_8]
.text:00000000000CDD48                 LSL             W26, W24, #0xC
.text:00000000000CDD4C                 MOV             W27, W24
.text:00000000000CDD50                 SBFIZ           X26, X26, #2, #0x20 ; ' '
.text:00000000000CDD54                 SBFIZ           X24, X24, #2, #0x20 ; ' '
.text:00000000000CDD58                 LDR             W4, [X23,#0x3C]
.text:00000000000CDD5C                 LDR             X3, [X23]
.text:00000000000CDD60                 LDR             X2, [X23,#8]
.text:00000000000CDD64                 SXTW            X25, W4
.text:00000000000CDD68                 LDR             X5, [X23,#0x10]
.text:00000000000CDD6C                 LSL             X1, X25, #4
.text:00000000000CDD70                 LDRSW           X6, [X23,#0x38]
.text:00000000000CDD74                 SUB             X7, X1, X25
.text:00000000000CDD78                 LDR             W9, [X3,X24]
.text:00000000000CDD7C                 LDR             W11, [X2,X24]
.text:00000000000CDD80                 ADD             X10, X7, X6
.text:00000000000CDD84                 LDR             W8, [X5,W4,SXTW#2]
.text:00000000000CDD88                 SUB             W14, W9, #0x20 ; ' '
.text:00000000000CDD8C                 LDR             X13, [X23,#0x18]
.text:00000000000CDD90                 SUB             W15, W11, #0x20 ; ' '
.text:00000000000CDD94                 LDR             X19, [X23,#0x28]
.text:00000000000CDD98                 MOV             W3, W8
.text:00000000000CDD9C                 LDR             X12, [X23,#0x30]
.text:00000000000CDDA0                 MADD            W16, W8, W15, W14
.text:00000000000CDDA4                 LDR             X17, [X13,X10,LSL#3]
.text:00000000000CDDA8                 ADD             X19, X19, X26
.text:00000000000CDDAC                 LDR             X1, [X23,#0x20]
.text:00000000000CDDB0                 MOV             X2, X19
.text:00000000000CDDB4                 ADD             X25, X12, X24
.text:00000000000CDDB8                 ADD             X0, X17, W16,SXTW
.text:00000000000CDDBC                 BL              FftCorr1
.text:00000000000CDDC0                 FCMP            S0, #0.0

It would appear that the result of the FftCorr1 function is returned in register S0.

How parameters and results are passed is specified in the ARM 64-bit Procedure Call Standard.

A short Godbolt example shows how a simple function float example(float) returns its result in S0.

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