There is no problem, the comment is simply informational.
The TMS320C6 is a DSP and like many DSPs the architecture is optimized for fast data processing. In particular, it has a very deep pipeline and the branches have not one or two, but up to five delay slots. You can see that after the
B .S2X A3 instruction there are five other instructions before the comment “BRANCH OCCURS” (in one case the fifth instruction is parallel/dual which is denoted by the
|| symbol). All these instructions are executed before the execution begins at the destination (A3 register value).
Because the register can in theory have any value, IDA did not print the destination address unlike the other cases.
BTW I would recommend looking at the disassembly for this processor in text (flat) mode since graphs may not always look nice with such deep delay slots.