I'm currently programming a x64 kernel and need to set the Apic mode to symmetric I/O Mode. The Multiprocessor Specification from Intel at Page 31 says that to enable this mode you have to write 01H to the IMCR memory register. The problem is that this memory register (has to be accessed over outb/inb) is absolutely nowhere documented. Can someone point me to the official spec where it's written down?
As I understand it the Multiprocessor Specification is the only Intel document that references this, with the following info
PIC Mode is software compatible with the PC/AT because it actually employs the same hardware interrupt configuration. As Figure 3-2 illustrates, the hardware for PIC Mode bypasses the APIC components by using an interrupt mode configuration register (IMCR). This register controls whether the interrupt signals that reach the BSP come from the master PIC or from the local APIC. Before entering Symmetric I/O Mode, either the BIOS or the operating system must switch out of PIC Mode by changing the IMCR. The IMCR is supported by two read/writable or write-only I/O ports, 22h and 23h, which receive address and data respectively. To access the IMCR, write a value of 70h to I/O port 22h, which selects the IMCR. Then write the data to I/O port 23h. The power-on default value is zero, which connects the NMI and 8259 INTR lines directly to the BSP. Writing a value of 01h forces the NMI and 8259 INTR signals to pass through the APIC. The IMCR must be cleared after a system-wide INIT or RESET to enable the PIC Mode as default. (Refer to Section 3.7 for information on the INIT and RESET signals.) The IMCR is optional if PIC Mode is not implemented. The IMCRP bit of the MP feature information bytes (refer to Chapter 4) enables the operating system to detect whether the IMCR is implemented.
Example use case can be found in linux kernel within APIC.c:
However these documents supersede the Multiprocessor specification and don't reference IMCR: