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I have recently learned that nop instruction is actually xchg eax, eax... what it does is basically exchanges eax with itself.

As far as CPU goes, does the exchange actually happen?

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There are several instructions, which could be used depending on the compiler. xchg eax, eax is byte code 90. It is a legit instruction, which takes up a single processing cycle. In addition, there are several other instructions, which could be used in place of xchg eax, eax:

lea eax, [eax + 0x00]    byte code 8D 40 00
mov eax, eax             byte code 89 C0

Since all of those instructions are different length, compiler chooses one of the most appropriate versions depending on alignment requirements.

Regarding compilers' choices, a few pointers:

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    but they are probably less "NOP-like" than the xchg is. Besides which, the documented multi-byte NOP is the "0f 1f /0" set. Jun 20 '13 at 19:16
  • The only other nop instruction is 0F 1F /0 which is NOP r/m16 and NOP r/m32 on supported CPUs. It may take anywhere from 3 to 9 bytes in x86-64, as per Intel doc (page 4-163). So even though you can use mov eax, eax and others an an alternative, it has a downside vs. real nop in that it blocks CPU pipeline and lacks other hardware optimizations that are implemented in the nop instruction.
    – ahmd0
    May 17 '18 at 21:45
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The short answer is "Yes." In fact, if you experiment by generating machine language op codes directly you will discover that there is a whole range of operations that are effectively NOPs, all of which take a single processor cycle to execute.

While they are not technically "Documented," you will find that very close to the 0x90,

  • XCHG EAX, EAX
  • XCHG EBX, EBX
  • XCHG ECX, ECX
  • XCHG EDX, EDX
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    I don't think this is is true. I think the non-EAX take more cycles (3 and not 1) and I think all the XCHG versions actually 0 the higher order 32 bits on a x86_64. stackoverflow.com/a/25053039/124486 Feb 6 '18 at 1:41

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