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I am starting to look a bit more precisely at ARM assembler and I looked up some dumps from objdump. I saw a lot of instruction (add is not the only one) with an extra s at the end (adds, subs, ...).

I looked a bit to the ARM documentation and it seems to mean something significant, but I can't figure out exactly what (the documentation I found about it seemed extremely obscure to me).

Has somebody some insight on what is the meaning of this extra s added at the end of some ARM instructions ?

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up vote 7 down vote accepted

Usual ADD doesn't update flags. ADDS does. See better documentation at arm infocenter. As it wrote there:

If S is specified, these instructions update the N, Z, C and V flags according to the result.

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This is about what I read in the documentation, but I have no idea of what flags they are speaking about. Could you be a bit more detailed about the flags that are touched and, maybe, give an example where it makes really a difference to use adds in place of add ? – perror May 4 '14 at 17:19
See updated answer. – w s May 4 '14 at 17:26
@perror If you want another concrete example, consider a loop while(--i){...}. One way to implement it is to have sub reg, #1 followed by an explicit compare to zero (which will set the Z zero flag when reg becomes 0), then a predicated branch. With subs reg, #1 the Z flag is implicitly updated, therefore no explicit comparison is required. – Iwillnotexist Idonotexist May 5 '14 at 3:19

The extra s character added to the ARM instruction mean that the APSR (Application Processor Status Register) will be updated depending on the outcome of the instruction.

The status register (APSR) contain four flags N, Z, C and V which means the following:

  • N == 0: The result is greater or equal to 0, which is considered positive, and so the N (negative) bit is set to 0.
  • Z == 1: The result is 0, so the Z (zero) bit is set to 1.
  • C == 1: We lost some data because the result did not fit into 32 bits, so the processor indicates this by setting C (carry) to 1.
  • V = 0: From a two's complement signed-arithmetic viewpoint, 0xffffffff really means -1, so the operation we did was really (-1) + 1 = 0. That operation clearly does not overflow, so V (overflow) is set to 0.

More information about the condition flags in the ARM architecture can be found here.

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One additional point: depending on the disassembler/settings, the Thumb-1 instructions (short, 16-bit encodings for a subset of instructions) may be displayed without the S suffix, even though they, in fact, do update flags. See Table 4-9 here. – Igor Skochinsky May 4 '14 at 18:55
Is it because it is the default behavior of the instruction in thumb mode, or the opcodes are really different but the mnemonic does not show up the difference ? – perror May 4 '14 at 19:02
The former. In Thumb-1, all ALU instructions set the flags and so I guess the creators dropped the suffix as "unnecessary". With Thumb-2, full equivalence with the ARM set was achieved and you can choose if you want to set flags or not. Thus the move to UAL and explicit S suffix. – Igor Skochinsky May 4 '14 at 20:05
Shouldn't the explanation to N == 0 be The result is greater than or equal to 0 ... ? – Guntram Blohm May 4 '14 at 21:50
@GuntramBlohm: Yes, you're right. It's fixed. – perror May 4 '14 at 22:12

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